1. Field of the Invention
The present invention relates to a synchronizing signal processing circuit for use in a monitor television, a display monitor and the like.
2. Description of the Prior Art
There are various types of synchronizing signals to be input to a display monitor etc. In one type, a horizontal synchronizing signal and a vertical synchronizing signal are input separately, and, in another type, they are input as a composite signal. Further, the synchronizing signals have amplitude of 1.0 to 5.0 V.sub.p-p and polarity of positive and negative. In order to process the synchronizing signals, the display monitor is provided with a synchronizing signal processing circuit having a polarity detection circuit for detecting polarity of the synchronizing signals. The output information from the polarity detection circuit is used to so waveform-shape the synchronizing signals that they always have the same amplitude and polarity. The output information is also used to perform control for changing a size of display area in response to the detected polarity, for example.
FIG. 1 is a circuit diagram showing a conventional synchronizing signal processing circuit. FIGS. 2A to 2D and FIGS. 3A to 3D show voltage waveforms at respective points A to D in the circuit shown in FIG. 1 in the case of positive polarity and amplitude of 1 V.sub.p-p and in the case of negative polarity and amplitude of 5 V.sub.p-p, respectively. Referring to the figures, a synchronizing signal is input through a coupling capacitor 10 to be supplied to a plus input of a comparator 12 having a minus input to which reference voltage V.sub.1 is applied. The comparator 12 compares the synchronizing signal with the reference voltage V.sub.1 to output a signal having constant amplitude and the same polarity as the input synchronizing signal. The output signal from the comparator 12 is supplied to a low-pass filter 14 formed by a resistor 14a and a capacitor 14b. The low-pass filter 14 serves as a polarity detector to output a low-level voltage signal in the case of positive polarity input or a high-level voltage signal in the case of negative polarity input. An exclusive OR circuit 16 receives the output signals from the comparator 12 and the low-pass filter 14 to output a synchronizing signal of negative polarity and constant amplitude regardless of polarity and amplitude of the input synchronizing signal.
FIG. 4 is a circuit diagram showing a conventional polarity detection circuit. FIG. 2E and FIG. 3E show voltage waveforms at a point E in the circuit shown in FIG. 4 in the case of positive polarity and amplitude of 1 V.sub.p-p and in the case of negative polarity and amplitude of 5 V.sub.p-p, respectively. Voltage waveforms at points A to C are similar to those shown in FIGS. 2A to 2C and FIGS. 3A to 3C. Referring to the figures, a comparator 18 receives an output signal from a low-pass filter 14 at its plus input to compare the same with reference voltage V.sub.2 applied to its minus input. The level of the reference voltage V.sub.2 is shown in FIG. 2C and FIG. 3C. Thus, the comparator 18 outputs a low-level voltage signal in the case of a positive polarity input synchronizing signal, as shown in FIG. 2E, or a high-level voltage signal in the case of a negative polarity input synchronizing signal, as shown in FIG. 3E.
The synchronizing signal processing circuit shown in FIG. 1 and the polarity detection circuit shown in FIG. 4 have following disadvantages:
First, if the input synchronizing signal has relatively small duty cycle, e.g. smaller than 1%, such as a vertical synchronizing signal, and relatively small amplitude, e.g. 1.0 V.sub.p-p, difference voltage .DELTA.V between the reference voltage V.sub.1 and the reference voltage of the input synchronizing signal after capacitive coupling through the capacitor 10 becomes very small to decrease noise margin.
Secondly, when there is no input signal, the comparator 12 receives the same voltage at its two inputs to output a signal of indefinite level, i.e. high-level or low-level, according to input offset voltage of the comparator 12. Therefore, output signals from the synchronizing signal processing circuit shown in FIG. 1 and the polarity detection circuit shown in FIG. 4 are also indefinite. This makes design of an circuit in the post-stage of these circuits difficult.
Thirdly, it is difficult to form these circuits as an IC, since the low-pass filter 14 serving as a polarity detector includes the capacitor 14b which needs capacitance more than 1 .mu.F to sufficiently depress a frequency of the horizontal or vertical synchronizing signal. If they are formed as an IC, the IC must have a terminal to externally connect the capacitor 14b. Further, response speed of the low-pass filter 14 is relatively slow, and hence it takes relatively long time to obtain a normal output when polarity abruptly varies.